Data carrier with detection means for detecting a change made of information stored with storing means

ABSTRACT

In a circuit ( 2 ) comprising a first memory means ( 5 ) for modifiable storage of information (I), the information (I) being modifiable by an ambient parameter of the circuit ( 2 ), which ambient parameter acts on the first memory means ( 5 ), there is firstly provided in the first memory means ( 5 ) a test memory area ( 7 ) for storing test information (TI) and there is secondly provided a second memory means ( 16 ) for unmodifiable storage of reference information (RI) and there is thirdly provided a detection means ( 19 ), to which detection means ( 19 ) there may be supplied the test information (TI) which may be read out from the first memory means and the reference information (RI) which may be read out from the second memory means ( 16 ) and which detection means ( 19 ) is designed, with the aid of the read-out test information (TI) and the read-out reference information (RI), to detect a modification of the originally stored test information (TI) brought about by an ambient parameter acting on the first memory means ( 5 ).

The invention relates to a data carrier comprising a circuit, whichcircuit comprises the following components, namely first memory means,which are designed for modifiable storage of information, theinformation being modifiable by an ambient parameter of the circuit,which ambient parameter acts on the first memory means.

The invention also relates to a circuit, which circuit comprises thefollowing components, namely first memory means, which are designed formodifiable storage of information, the information being modifiable byan ambient parameter of the circuit, which ambient parameter acts on thefirst memory means.

Such a data carrier of the type described above in the first paragraphand such a circuit of the type described above in the second paragraphare known from document DE 42 05 567 A1.

The known data carrier, which is designed for contactless communicationwith a read/write station and which comprises the known circuit,comprises first memory means which are designed for modifiable storageof information. The data carrier also comprises an access control meansand a bus connection between the first memory means and the accesscontrol means, wherein, in normal operation, the information stored inthe first memory means may be modified by desired electrical accessingof the access control means via the bus connection to the first memorymeans.

In the case of the known data carrier, the problem arises that theinformation stored in the first memory means can be modified not only bydesired access via the bus connection but also in another manner, namelyby the undesired effect of an ambient parameter acting on the firstmemory means, such as for example a short-wave light or an electricalfield or a high temperature. A modification of the stored informationbrought about in this way may lead to complete failure of the datacarrier or to dangerous malfunctioning of the data carrier or maypossibly even be exploited for criminal purposes.

It is an object of the invention to eliminate the above-listed problemsassociated with a data carrier of the type described above in the firstparagraph and a circuit of the type described above in the secondparagraph and to provide an improved data carrier and an improvedcircuit.

To achieve the above-described object with regard to a data carrier ofthe type described above in the first paragraph, the first memory meanscomprise a test memory area, which is provided for storing testinformation, and second memory means are provided which are designed forunmodifiable storage of reference information, and detection means areprovided, to which the test information which may be read out from thefirst memory means and the reference information which may be read outfrom the second memory means may be supplied and which are designed,with the aid of the read-out test information and the read-out referenceinformation, to detect a modification of the originally stored testinformation brought about by an ambient parameter acting on the firstmemory means.

To achieve the above-described object with regard to a circuit of thetype described above in the second paragraph, the first memory meanscomprise a test memory area, which is provided for storing testinformation, and second memory means are provided which are designed forunmodifiable storage of reference information, and detection means areprovided, to which the test information which may be read out from thefirst memory means and the reference information which may be read outfrom the second memory means may be supplied and which are designed,with the aid of the read-out test information and the read-out referenceinformation, to detect a modification of the originally stored testinformation brought about by an ambient parameter acting on the firstmemory means.

The advantage is thereby achieved that an unambiguous statement as towhether the information stored in the first memory means has or has notbeen modified by an ambient parameter, and consequently in relation tothe invalidity or validity respectively of the information stored in thefirst memory means may be made in a reliable and reproducible manner. Inaddition, the advantage is achieved that modification of the storedinformation which is caused unintentionally, i.e. accidentally by anambient parameter modifying the originally stored information, orintentionally, i.e. for purely technical or even criminal reasons, maybe detected virtually one hundred percent reliably because the testinformation and the information are stored together in the first memorymeans and therefore are jointly exposed to the ambient parameter actingon the first memory means and are jointly subject to a modificationcaused thereby.

A solution according to the invention may for example be characterizedin that the test information or the reference information are stored inencrypted manner for security reasons and that the detection meanscomprise decrypting means for decrypting at least one of the twoinformation elements. In addition, a solution according to the inventionmay be characterized in that the detection means may be designed tocompare a representation of the test information with a representationof the reference information, which two representations may becalculated by suitable calculating methods. In addition, the detectionmeans may be designed to perform a so-called coincidence method. Inaddition, the detection means may be realized as correlator. However, ithas proven particularly advantageous for the features as claimed inclaim 2 or claim 7 to be provided. The advantage is thereby achievedthat a reliable statement with regard to a possible modification andconsequently the possible invalidity of the information stored in thefirst memory means may be made by a quick comparison, which may even beperformed purely at a hardware level.

In the case of a solution according to the invention, it has also provenadvantageous for the features as claimed in claim 3 or claim 8 to beprovided. In this way, the advantage is achieved that, during a testingstate time period, as provided for example during or after production ofthe circuit, functioning of the detection means may be prevented. Inaddition, the advantage is achieved that functioning of the detectionmeans may be started at a well-defined time and that this functioning ofthe detection means can no longer be cancelled once started, whereby,from this time onwards, any modification of the information stored inthe first memory means brought about by an ambient parameter forwhatever reason may be reliably detected.

In the case of a solution according to the invention, it has also provenadvantageous for the features as claimed in claim 4 or claim 9 to beprovided. In this way, the advantage is achieved that, after detectionof a modification of the test information brought about by the ambientparameter acting on the first memory means, operating behavior may beinfluenced to the effect that any criminally motivated use of thecircuit or of the data carrier is reliably prevented.

In the case of a solution according to the invention, it has also provenadvantageous for the features as claimed in claim 5 or claim 10 to beprovided. In this way, the advantage is achieved that the testinformation is represented by a bit sequence which comprises only bitswith logical values which do not occur during production of the firstmemory means or are not present after a modification of the informationstored in the first memory means brought about by the action of anambient parameter on the first memory means, wherein it may bementioned, for the sake of completeness, that in both cases each bit ofthe first memory means represents either a logical one or a logicalzero.

In the case of a solution according to the invention, it has also provenadvantageous for the features as claimed in claim 11 to be provided. Inthis way, the advantage is achieved that the circuit may be produced aseconomically as possible on a large scale.

The above-stated aspects of the invention and further aspects thereofemerge from the examples of embodiment described below and are explainedwith reference to these examples of embodiment.

The invention will be further described with reference to examples ofembodiments shown in the drawings to which, however, the invention isnot restricted.

FIG. 1 is a schematic representation, in the form of a block diagram, ofa data carrier according to a first example of embodiment of theinvention.

FIG. 2 shows a data structure for storing information in first memorymeans of a data carrier according to the invention, in accordance withthe first example of embodiment of the invention.

FIG. 3 shows a data structure for storing information in the firstmemory means of a data carrier according to the invention, in accordancewith a second example of embodiment of the invention.

FIG. 1 shows a data carrier 1, which is designed for contactlesscommunication with a communications station not illustrated in FIG. 1.To this end, the data carrier 1 is designed to receive a signal S fromthe communications station in contactless manner, wherein the signal isformed by a high-frequency carrier wave and wherein the data carrier 1may be supplied with power by means of the signal S. In addition,interrogation information may be communicated from the communicationsstation to the data carrier 1 by means of the signal S, wherein thesignal exhibits amplitude modulation of the carrier wave. In addition,response information may be communicated from the data carrier 1 to thecommunications station by means of the signal S, wherein the signal Sexhibits load modulation of the carrier wave which may be brought aboutby the data carrier 1. It should be mentioned that phase or frequencymodulation of the carrier wave may also be provided for communicationpurposes.

The data carrier 1 comprises an electrical integrated circuit 2. Thecircuit 2 comprises components of transceiver means 3, which aredesigned to receive the signal S. To this end, the transceiver means 3exhibit a transmission coil configuration, not shown in FIG. 1, which iscoupled to the circuit 2, such that the signal S arising at thetransmission coil configuration may be supplied to the circuit 2. Thetransceiver means 3 are additionally designed, using the signal S, togenerate a supply voltage V relative to a reference potential GND forthe circuit 2. The transceiver means 3 are additionally designed todemodulate the in this case modulated received signal S and to outputinterrogation data RD communicated by means of the modulated receivedsignal S. The transceiver means 3 are additionally designed to receiveresponse data AD and, for the purpose of transmitting the response dataAD, for load modulation of the in this case unmodulated received signalS.

The circuit 2 further comprises data processing means 4, which take theform of a hard-wired logic circuit. The data processing means 4 may alsotake the form of a microcomputer. The data processing means 4 aredesigned to receive the interrogation data RD and to process theinterrogation data RD and, as a function of the interrogation data RD,to generate the response data AD and to output the response data AD tothe transceiver means 3.

The circuit 2 comprises first memory means 5, which are designed formodifiable storage of information I, the information I being modifiableby an ambient parameter of the circuit 2, which ambient parameter actson the first memory means 5. In the present case, the first memory means5 take the form of an EEPROM. It should be mentioned at this point thatthe first memory means 5 may, however, also take the form of othernon-volatile read/write memories, such as for example an EPROM, a FLASHmemory or a magnetic RAM. According to the invention, as soon as thefirst memory means 5 are exposed to an ambient parameter, such as forexample a short-wave light, a high temperature of a relatively strongelectromagnetic field, modification of the stored information I isbrought about by this ambient parameter. This modification usuallydeletes the information I or at least renders it unusable. The firstmemory means 5 comprise a first user memory area 6 and a test memoryarea 7. The test memory area 7 is provided for storage of testinformation TI. The user memory area 6 is provided for storage of userinformation UI. The information I storable in the first memory means 5is consequently formed of the user information UI and the testinformation TI. The information I is represented by a large number ofbits, wherein the bits are organized in a so-called sector-oriented datastructure.

FIG. 2 shows such a sector-oriented data structure for storing theinformation I in the first memory means 5. The first user memory area 6comprises a large number of data sectors, a first data sector 8 and asecond data sector 9 and a third data sector 10 being shown asrepresentatives thereof. Each of the large number of data sectorscomprises a sector access control byte 11 and four sector data bytes 12,13, 14 and 15, which situation is illustrated by the first data sector8, acting as representative for the large number of data sectors. Thesector access control byte 11 is provided for storing control data, bymeans of which access to the four sector data bytes 12, 13, 14 and 15 isenabled or prevented. The sector data bytes 12, 13, 14 and 15 areprovided for storing user data for representing the user information UI.The test memory area 7 is formed by a test information byte, which islocated at the highest memory address of the first memory means 5. Itshould be mentioned in this context that any other memory address mayalso be provided therefor within the first memory means 5. It shouldadditionally be mentioned that the stored information I does not have tostored exclusively in the form of bytes, but may also be stored aslogical nibbles each consisting of 4 bits or as logical words eachconsisting of 16 bits or by means of any other bit grouping.

The circuit 2 illustrated in FIG. 1 further comprises two memory means16, which take the form of a ROM. The second memory means 16 comprise asecond user memory area 17 and a reference memory area 18. The seconduser memory area 17 is provided for the unmodifiable storage ofconstants, which are required for processing the data by means of thedata processing means 4 or for generating response data AD, which willnot be looked at in any more detail below, however. The reference memoryarea 18 is designed for unmodifiable storage of reference informationRI. As with the first memory means 5, the constants and the referenceinformation RI are represented by a large number of bits, which areorganized in a data structure which is similar to the data structure inthe first memory means 5. It should be mentioned, however, that the datastructure present within the second memory means 16 may in principle beindependent, i.e. different from the data structure present in the firstmemory means 5.

The circuit 2 further comprises detection means 19, to which the testinformation TI which may be read out from the first memory means 5 andthe reference information RI which may be read out from the secondmemory means 16 may be supplied and which are designed, with the aid ofthe read-out test information TI and the read-out reference informationRI, to detect a modification of the originally stored test informationTI brought about by an ambient parameter acting on the first memorymeans 5. To this end, the detection means 19 comprise first comparisonmeans 20, which are designed to access the first memory means5—specifically the test memory area 7—for the purpose of reading out thetest information TI. The first comparison means 20 are additionallydesigned to access the second memory means 16—specifically the referencememory area 18—for the purpose of reading out the reference informationRI. The first comparison means 20 are additionally designed to comparethe stored test information TI with the stored reference information RI.The detection means 19 are additionally designed to generate and outputan indicator signal DS, which indicator signal DS is provided toindicate that modification of the originally stored test information TIbrought about by an ambient parameter acting on the first memory means 5has occurred, wherein the indicator signal DS is formed by a comparisonresult of the first comparison means 20 obtained as a result of thecomparison of the test information TI with the reference information RI.

It should be mentioned that the indicator signal DS may also take theform of a representation of the comparison result. It shouldadditionally be mentioned that the indicator signal DS may also provideperpetual indication of the modification of the originally stored testinformation TI. This is the case, for example, when the indicator signalDS represents the content of a memory cell taking the form of a PROM orwhen the indicator signal DS represents a conductivity state of asingle-use fuse. Detection of the modification of the originally storedtest information TI may be performed in the present case each time asupply voltage V sufficient for data processing occurs, prior to saiddata processing. It should be mentioned, however, that said detectionmay also be performed periodically or non-periodically during dataprocessing.

The data processing means 4 are connected to the first memory means 5and the second memory means 16 via a so-called bus connection B,wherein, with the aid of the bus connection B, the user information UImay be written to the first user memory area 6 of the first memory means5 or read out from said first user memory area 6 and wherein informationI representing the stored constants may be read out from the second usermemory area 17. When the indicator signal DS is received, the dataprocessing means 4 are designed to prevent access to the first memorymeans 5 and/or the second memory means 16. In addition, the dataprocessing means 4 are designed to generate and output response data AD,which indicate that a modification of the originally stored testinformation TI brought about by an ambient parameter acting on the firstmemory means 5 has occurred. Once the indicator signal DS has beenreceived, the data processing means 4 are stopped permanently fromcontinuing to process data. Accordingly, the circuit 2 is designed toinfluence its operating behavior as a function of the indicator signalDS.

The response data AD may be communicated to the read/write station bythe communication means 3, where they may be output, optionally in theform of visible display information, to a user of the data carrier 1.

The circuit 2 also comprises enabling means 21, which are providedirreversibly to enable functioning of the detection means 19. Theenabling means 21 are designed, for this purpose, to generate and outputa status signal SC, which may represent an enabling state or aninhibiting state. The first comparison means 20 of the detection means19 are designed to receive the status signal SC, wherein, if theenabling state is represented, functioning of the detection means 19 isenabled and wherein, if the inhibiting state is represented, functioningof the detection means 19 is not enabled. Accordingly, the detectionmeans 19 are designed to cooperate with the enabling means 21.

For the purpose of generating the status signal SC, the enabling means21 comprise a test signal generator 22, which is designed to output atest signal SS to a first saw bow part 23, which first saw bow part 23constitutes a component of the circuit 2. The enabling means 21 furthercomprise second comparison means 24, which are designed to receive thetest signal SS outputtable to the first saw bow part 23. The secondcomparison means 24 are additionally connected to a second saw bow part25, and are designed to receive a comparison signal SS′ suppliable bymeans of the second saw bow part 25 of the circuit 2. The secondcomparison means 24 are additionally designed to compare the test signalSS with the comparison signal SS′ and, if the test signal SS isidentical to the comparison signal SS′, to output a status signal SCrepresenting the inhibiting state. If the test signal SS is notidentical to the comparison signal SS′, the second comparison means 24are designed to output a status signal SC representing the enablingstate.

The first saw bow part 23 and the second saw bow part 25 are componentsof a “saw bow”, which saw bow, in the case of an integrated electricalcircuit 2 arranged within a wafer, forms an electrically conductiveconnection between the first saw bow part 23 and the second saw bow part25 within a sawing zone of the wafer, such that it may be establishedfrom the circuit 2 that the circuit 2 is arranged within the wafer andthat tests may be performed which are designed not to be performableafter separation of the circuit 2 from the wafer, specifically in theevent of the circuit 2 being sawn out of the wafer. If the circuit 2 isdetached from the wafer, the saw bow is diced, such that, when thecircuit 2 has been detached from the wafer, only the first saw bow part23 and the second saw bow part 25 remain within the circuit 2 ascomponents of the original saw bow. Accordingly, when the saw bow isintact, the comparison signal SS′ is formed by the test signal SS,whereas, when the saw bow has been cut through or destroyed, leavingonly the first saw bow part 23 and the second saw bow part 25 within thecircuit 2, the two signals SS and SS′ are not identical to one another.Such a saw bow is known from patent document WO 02/09153 A2, thedisclosure of which is deemed to be included herein.

In the data structure of the first memory means 5, illustrated in FIG.3, the test memory area 7 is distributed over each of the data sectors,such that each data sector has its “own” test information TI assigned toit, which is represented by a test information bit pair BP, BPA and BPBrespectively, the first three data sectors 8, 9 and 10 being illustratedas representatives of the large number of data sectors. In each sectoraccess control byte 11, 11A and 11B, two bits are reserved for the testinformation TI, TIA and TIB respectively assigned to the respective datasector 8, 9 and 10. In this way, the advantage is achieved that, even ifthe ambient parameter acts in isolated manner on one zone of the firstmemory means 5, a modification of the originally stored test informationTI, TIA or TIB respectively brought about by an ambient parameter actingon the first memory means 5 may be detected virtually one hundredpercent reliably. However, it should be mentioned at this point thatmore than two bits may be provided within each data sector 8, 9 and 10to represent the respective test information TI, TIA and TIBrespectively and that the individual bits do not have to be arrangednext to one another.

In the two examples of embodiment described above, reference was made toa data structure based on data sectors. It should be mentioned, however,that any other data structure may also be used for the first memorymeans 5.

The mode of operation of the data carrier 1 is explained below withreference to an example of application of the data carrier 2 accordingto FIG. 1. In accordance with this example of application, it should beassumed that, at a point in time when the circuit 2 of the data carrier1 was located within a wafer at a semiconductor manufacturer's and thesaw bow was intact, of which saw bow the first saw bow part 23 and thesecond saw bow part 25 constitute components of the circuit 2 connectedtogether electrically conductively, test information, which isrepresented by the bit sequence “01010110”, was stored in the testmemory area 7 of the first memory means 5. It should also be assumedthat only the first sector 8 is used of the large number of data sectorsand that control data were stored in the sector access control byte 11which enable encrypted access to the four sector data bytes 12, 13, 14and 15. The four sector data bytes 12, 13, 14 and 15 are provided forstoring user data representing the user information UI, which user dataallow unambiguous identification of a user of the data carrier 1. Theuser data may be stored in the user data memory area 6 by a serviceprovider, which provides a user with the data carrier 1, using a codefor encrypted access to the four sector data bytes 12, 13, 14 and 15. Itshould also be assumed that a bit sequence identical to the bit sequencestored in the test memory area 7 was stored in the reference memory area18. The circuit 2 was then severed from the wafer by sawing therefrom,wherein the saw bow was destroyed and the two saw bow parts 23 and 25remain electrically isolated from one another within the circuit 2. Fromthis point in time, the first test information TI can no longer bemodified.

After delivery to the service provider, the user information UI requiredto identify the user is stored in the data carrier 1, using the codesubmitted to the service provider by the semiconductor manufacturer,whereupon the data carrier 1 may be used to enable access to an area ofan industrial company with restricted access.

The data carrier 1 in circulation is exposed during use to a very widerange of environmental influences, which environmental influences arecharacterized by an ambient parameter of the data carrier 1 or thecircuit 2. In the present case, it should be assumed that the datacarrier 1 is brought inadvertently into the vicinity of a high-frequencywelding apparatus, wherein a powerful high frequency field generated bymeans of the high-frequency welding apparatus deletes the contents ofthe first memory means 5. The memory contents are returned to an“original state”, as was present originally after production of thefirst memory means 5 and in which the first memory means 5 comprise onlybits which represent a logical one.

The user, who does not or indeed cannot notice this deletion of thecontents of the first memory means 5, introduces the data carrier 1 intoa communications area of a read/write station, to gain access to therestricted access zone. The signal S output by the read/write station,which signal S is formed by a high-frequency carrier wave, which isprovided for communication with the data carrier 1 and for supplying thedata carrier 1 with power, is received by the transceiver means 3. Firstof all, the supply voltage V for the circuit 2 is generated by thetransceiver means 3.

As soon as the supply voltage V has exceeded a threshold value, the testsignal SS is generated by the test signal generator 22 and output to thefirst saw bow part 23 and the second comparison means 24. At the sametime, the second comparison means 24 receive the comparison signal SS′,which does not match the test signal SS because the saw bow exists onlyin part within the circuit 2. The second comparison means 24 thengenerate the status signal SC representing the enabling state and outputthis status signal SC to the first comparison means 20.

At the first comparison means 20, the status signal SC representing theenabling state results in the first comparison means 20 accessing thefirst memory means 5 and reading out the test information TI modified bythe ambient parameter, which test information TI is represented at thispoint by the bit sequence “11111111”. The comparison means 20 alsoaccess the second memory means 16 and read out the originally storedreference information RI, which cannot be modified by the ambientparameter and which takes the form of the bit sequence “01010110”. Thetest information TI is then compared with the reference information RIby the first comparison means 20, wherein the comparison reveals that amodification of the originally stored test information TI has beenbrought about by an ambient parameter acting on the first memory means,because the test information TI does not match the reference informationRI. This detection of the modified test information TI is indicated bymeans of the indicator signal DS to the data processing means 4, therebyputting a stop to any future processing in the data processing means 4beyond the generation and outputting of response data AD, which responsedata AD represent the meaning of the indicator signal DS. The responsedata AD are communicated by the transceiver means 3 to the read/writestation and are there interpreted to the effect that the data carrier 1has become invalid because the originally stored test information TI hasbeen modified and it may therefore be assumed that any other informationI stored using the first memory means 5 has also in all probability beenmodified.

The provision of these measures according to the invention in the caseof the data carrier 1 or the circuit 2 has proven advantageous becauseunlawful use of the first data sector 8 may thereby be preventedvirtually one hundred percent reliably, despite the contents of thesector access control byte 11 having been deleted, which could in itselfopen the way to fraudulently motivated use of the data carrier 2.

In the present case, use of the circuit 2 according to the invention ina data carrier 1 according to the invention has been described. Itshould be mentioned, however, that the circuit 2 according to theinvention may also be used in a cell phone or a personal computer, forexample. In this context, it should be mentioned that the circuit 2 maycomprise a memory chip which includes the first memory means 5, thesecond memory means 16 and the detection means 19 and that such a memorychip may be used, for example, in a so-called SIM module, which SIMmodule is currently used in cell phones to identify a user. It shouldalso be mentioned in this context that, in addition to the first memorymeans 5 and the second memory means 16 and the detection means 19, thecircuit 2 according to the invention may also comprise a microprocessoror interface chips, such that a microcontroller may be provided, forexample, by means of the circuit 2 according to the invention.

It should also be mentioned that the transceiver means 3 of the datacarrier 1 may also take the form of an antenna configuration.

It should also be mentioned that the transceiver means 3 may be designedfor capacitive or optical communication.

It should additionally be mentioned that the data carrier 1 may also bedesigned for conventional contact communication.

It should additionally be mentioned that the data carrier 1 may alsocomprise its own power supply, which may take the form for example of atleast one battery or one solar cell configuration.

It should be mentioned that the enabling means 21 may take the form of abit of a once-programmable PROM memory cell, wherein the PROM memorycell is programmed after completion of manufacturing and testing of thecircuit 2 and prior to delivery of the circuit 2 to a customer. Alogical value represented by this bit constitutes the state of theenabling means 21 which enables functioning of the detection means 19.In this context, it should also be mentioned that a bit pattern may alsobe provided instead of a single bit. If the second memory means 16 takethe form of a PROM, at least one memory cell of this PROM may also beused to provide the enabling means 21.

It should additionally be mentioned that, if the enabling means 21 takethe form of once-programmable means, such as for example a PROM or afuse, the enabling means 21 may be programmed to enable the detectionmeans 19 not by a manufacturer of the circuit 2 but by a data carriermanufacturer, who produces the data carrier 1 using the circuit 2, or bya service provider, which delivers the data carrier 1 to an end user.

It should be additionally be mentioned that the enabling means 21 maytake the form of a fuse provided in the circuit 2, wherein the fuse isfused prior to delivery of the circuit 2 to a customer and wherein thefused state of the fuse, i.e. the non-conductive state of the fuse,constitutes the state of the enabling means 21 which enables functioningof the detection means 19.

It should additionally be mentioned that the second memory area 16 maybe present, like the data processing means 4, as part of a hard-wiredlogic circuit. In this context, it should additionally be mentioned thatthe second memory means 16 may also take the form of a program memory ofa microcomputer, wherein the reference information RI may also take theform of part of a program code. It should additionally be mentioned thatthe second memory means 16 may be provided solely for storage of thereference information RI.

It should additionally be mentioned that the test information TI and thereference information RI may be read out from the relevant memory means5 and 16 using the data processing means 4 and supplied to the detectionmeans 19.

It should additionally be mentioned that the indicator signal DS mayalso be outputtable to the two memory means 5 and 16 and that at leastone of the two memory means 5 and 16 may be designed to influence itsaccessibility as a function of the indicator signal DS. One possibleembodiment of the invention may be characterized in that access is nolonger possible to either of the memory means 5 and 16 when theindicator signal DS is present, indicating a modification of theoriginally stored test information TI.

It should additionally be mentioned that the indicator signal DS mayalso be outputtable to the transceiver means 3 and that the transceivermeans 3 may be designed to influence their communicating capacity as afunction of the indicator signal DS.

It should additionally be mentioned that, in the first memory means 5,hardware-enclosed memory areas may be provided for in each case oneapplication and that each of these memory areas may comprise its owntest information TI.

1. A data carrier comprising a circuit, which circuit comprises thefollowing components, namely first memory means, which are designed formodifiable storage of information, the information being modifiable byan ambient parameter of the circuit, which ambient parameter acts on thefirst memory means, characterized in that the first memory meanscomprise a test memory area, which is provided for storing testinformation, and second memory means are provided which are designed forunmodifiable storage of reference information, and detection means areprovided, to which the test information which may be read out from thefirst memory means and the reference information which may be read outfrom the second memory means may be supplied and which are designed,with the aid of the read-out test information and the read-out referenceinformation, to detect a modification of the originally stored testinformation brought about by an ambient parameter acting on the firstmemory means.
 2. A data carrier as claimed in claim 1, characterized inthat the detection means comprise comparison means for comparing thestored test information with the stored reference information.
 3. A datacarrier as claimed in claim 1, characterized in that enabling means areprovided for the purpose of irreversibly enabling functioning of thedetection means, and the detection means are designed to cooperate withthe enabling means.
 4. A data carrier as claimed in claim 1,characterized in that the detection means are designed to generate andoutput an indicator signal, which indicator signal is provided toindicate a modification of the originally stored test informationbrought about by an ambient parameter acting on the first memory meansand the circuit is designed to influence its operating behavior as afunction of the indicator signal.
 5. A data carrier as claimed in claim1, characterized in that the test information is formed of at least twobits, which at least two bits differ from one another with regard totheir logical value.
 6. A circuit, which circuit comprises the followingcomponents, namely first memory means, which are designed for modifiablestorage of information, the information being modifiable by an ambientparameter of the circuit, which ambient parameter acts on the firstmemory means, characterized in that the first memory means comprise atest memory area, which is provided for storing test information, andsecond memory means are provided which are designed for unmodifiablestorage of reference information, and detection means are provided, towhich the test information which may be read out from the first memorymeans and the reference information which may be read out from thesecond memory means may be supplied and which are designed, with the aidof the read-out test information and the read-out reference information,to detect a modification of the originally stored test informationbrought about by an ambient parameter acting on the first memory means.7. A circuit as claimed in claim 6, characterized in that the detectionmeans comprise comparison means for comparing the stored testinformation with the stored reference information.
 8. A circuit asclaimed in claim 6, characterized in that enabling means are providedfor the purpose of irreversibly enabling functioning of the detectionmeans, and the detection means are designed to cooperate with theenabling means.
 9. A circuit as claimed in claim 6, characterized inthat the detection means are designed to generate and output anindicator signal, which indicator signal is provided to indicate amodification of the originally stored test information brought about byan ambient parameter acting on the first memory means, and the circuitis designed to influence its operating behavior as a function of theindicator signal.
 10. A circuit as claimed in claim 6, characterized inthat the test information is formed of at least two bits, which at leasttwo bits differ from one another with regard to their logical value. 11.A circuit as claimed in claim 6, characterized in that the circuit takesthe form of an integrated circuit.